Metal oxide semiconductor field effect transistors (MOSFETs) often experience parasitic capacitance that may degrade the performance of the transistor. The source and drain of a transistor are typically adjacent to the transistor substrate. The interface between the source and drain regions and the substrate, however, often form depletion zones that result in parasitic capacitance. Known methods of reducing this form of parasitic capacitance call for using an implantation process to widen the transistor channel or for reducing the size of the source and/or drain regions. These known methods, however, do not satisfactorily reduce parasitic capacitance.